A smaller die size isn't always better. In fact, it can significantly increase your cost per wafer if special care isn't give during the design process.
12
11
Infinity Fabric 4 and custom silicon, CDNA 3 MI300 specifications, AMD CPU area efficiency, XDNA and AIE, and 2023 EPS estimates
5
9
Tangible bi-partisan solutions for solving a national security crisis.
52
24
Apple announced their new 20 billion transistor M2 SoC at WWDC. Unfortunately, it’s quite a minor uplift in performance in some areas such as CPU…
20
3
TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony's Leading 1-Micron Pitch Hybrid Bonding…
3
We break through the marketing fluff of Ampere. We also did a cost comparison of Ampere's Altra and Altra Max to AMD Milan and Intel Icelake. We also do…
1
2
Die shot analysis shows 40% area reduction on identical structures from Intel 7 to Intel 4. Analysis on Redwood Cove and Crestmont architecture, Foveros…
1
1
We had the chance to ask Pat Gelsinger about Intel's software strategy. His response was quite shocking. In our various discussions with other Intel…
15
3
See all