Thanks Dylan. How does sharing across "many" CPUs work? You get multiple Leo-P which connect to each other ? I got impression that 1 Leo P x16 will handle 2 CPUs (or maybe more with lower lanes but that will be slower ?)
Side note- Montage Technologies actually delivered the first ASIC memory expander (Gen5 CXL.io w/ DDR4/DDR5 combo controller) back in April’22. This is a fully functional part not an FPGA prototype. Their first sku is focused on the memory expansion module market
Is CXL (memory expansion/pooling) a capability that could be incorporated directly into CPUs and potentially other chips? Or is the required silicon too large to be incorporated and requires an external chip?
Thanks Dylan. How does sharing across "many" CPUs work? You get multiple Leo-P which connect to each other ? I got impression that 1 Leo P x16 will handle 2 CPUs (or maybe more with lower lanes but that will be slower ?)
Side note- Montage Technologies actually delivered the first ASIC memory expander (Gen5 CXL.io w/ DDR4/DDR5 combo controller) back in April’22. This is a fully functional part not an FPGA prototype. Their first sku is focused on the memory expansion module market
Is CXL (memory expansion/pooling) a capability that could be incorporated directly into CPUs and potentially other chips? Or is the required silicon too large to be incorporated and requires an external chip?