11 Comments
Jun 20, 2022Liked by Dylan Patel

The chiplet would be laid out in a more sensible proportion, using the full 26mm width of the reticle as much as possible, and dividing the height by half, plus the overhead for interconnect. So the tool throughput will drop more like 10% (counting extra stepping movements and extra area), not 87%.

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"here is an old ASML slide the topic"

"here is an old ASML slide ON the topic"

"The evolution lithography spending versus deposition versus "

"The evolution OF lithography spending versus deposition versus "

"Let’s assume this foundry WHICH sells these wafers for ~$17,000 with a ~50% gr"

"Let’s assume this foundry sells these wafers for ~$17,000 with a ~50% gr"

Not sure about the last one. Great content as always

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Googled some die sizes, and it seems like the most inefficient design is Navi 22, 18x18mm, can only fit one die per mask. That's like, 37% mask utilization.

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The lithography tool then exposes through the photomask to print features on the wafer at 4x magnification. —> shouldn’t it read “at 4x reduction”? As the features on the mask are reduced to a smaller exposure field on the wafer

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While the article raises a number of valid points, I don't think that this argument is supported:

> "The decision of chiplet vs monolithic becomes a lot more difficult now. Once you account for packaging costs, it is very likely the monolithic die is cheaper to fabricate."

If this were true, then why are chiplets becoming more and more popular?

It's not as if AMD, Intel and Nvidia didn't have people modelling this, too. The fact that we're nevertheless seeing more and more of chiplet designs would suggest that their models point to chiplets design still being cheaper.

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