TSMC 3nm Wafer Shipments Pushed Into Q1 2023, 2.5 Years After N5 | TSMC 2nm, Samsung 2nm, And Intel 20A Battle It Out In 2025

Oct 14, 2021

TSMC had some major announcements this morning. The most important being their comments on shortages and their N3 process node. To get the band aid ripped off first, TSMC says they are fully booked through 2022. People concerned about the semiconductor market going into a downturn need to relax a bit. Back to the big news, SemiAnalysis has been hearing murmurings about TSMC’s N3 having poor yields, poor metal stack performance, being very expensive, and being too late for Apple’s 2022 iPhone. These can’t be confirmed, but we can confirm that TSMC N3 is now shipping in Q1 2023.

The second half of 2022 will be our mass production, but you can expect the revenue will be seen in the first quarter of 2023 because it takes a long tech cycle time to have all those wafers out.
Dr. C. C. Wei – TSMC CEO

While some outlets may call it a “delay” that isn’t technically true. TSMC has always high-volume manufacturing will begin in the 2nd half of 2022. While this is still the story, the start of production is not the same as shipments. TSMC recognizes revenue when they ship the product out of their fabs to partners. These comments are very clear, TSMC is not shipping 3nm until 2023. This would be 2.5 years after N5 began shipping to customers which was Q3 of 2020.

This as we reported, is too late for the new iPhone. The primary reasons TSMC has gave 3 months ago was that the technology is very complicated, and they agreed with a customer to ramp later. The comment very much reads like Apple collaborated with TSMC and agreed not to risk production issues and stick with N5/N4.

About 3 to 4 months is a delay as compared with 5-nanometer. Yes, 3-nanometer technology actually is very complicated and in both processing technology and also the customers' product design. So we work with a customer, and finally, we decided to ramp up in the second half of next year.
Dr. C. C. Wei – TSMC CEO

If we tie these statements together, it very much sounds like despite a 3-4 month delay in production start date, there is a ~6 month delay in wafer shipments for N3. The reasoning is that 3nm has long cycle times. Essentially, as we continue to scale to newer process technologies, the number of process steps required to manufacture the chip skyrockets. For example, with EUV, there is a big throughput problem.

TSMC N3 will have about 30-35 EUV exposures per wafer. A TSMC fab with 10 $150M EUV machines running N3 wafers would only be capable of ~15,000 wafers per month at current power output and uptime rates. Lithography is but one step in the magical process of manufacturing chips, and other steps also explode in complexity. As such the cycle time for N3 has increased from about 3 months on N5 to much higher.

On the path to high volume manufacturing, there is a stage known as risk production. It generally starts a year before high volume manufacturing.

N-3 risk production is scheduled in 2021
Dr. C. C. Wei – TSMC CEO

We generally aren’t sticklers for grammar and tensing as everyone is human and makes mistakes, but SemiAnalysis is like a fly gravitating to sugar here. On October 14th 2021, TSMC said risk production IS SCHEDULED in 2021. This implies they have not begun risk production yet. Splitting hairs here, but the 3-4 month delay stated 3 months ago may be closer to 5 or 6 now.

N3 costs definitely it is higher than N5. That is because of technical complexity and we have to use many new pieces of equipment which is -- cost higher.
Dr. C. C. Wei – TSMC CEO

TSMC minced no words when talking about per wafer costs. SemiAnalysis often shocked people years ago when we discussed N7 wafers being roughly $10,000 each. N5 is even more eye popping at around $16,500, meaning the cost per transistor is up significantly. We are now hearing that N3 is above $20,000. While Mediatek and Qualcomm may jump to the N3 for smartphones before Apple, this high cost and other rumored issues may put them off. It is important to note that customers and their various agreements will differ in their per wafer cost.

Alongside these major nodes, TSMC always has nodelets. Process nodes such as N7+, N7P, N6, N5P, and N4 are all recent examples of nodelets. They don’t bring anything earth shattering over the major nodes of N7 and N5, but they do move the needle. Most N7 chips shipping are actually N7P. TSMC states that half of N7 volume will be N6 at the end of the year. The same applies to N5. N5 vanilla is a very rarely used node outside of Apple. The vast majority of new designs including the new A15, AMD, Marvell, and Nvidia are going to be N5. Mediatek will be skipping these nodes altogether and going straight to N4.

A bit of rambling on the background, but the point here is that TSMC usually goes normal node (N7 / N5) to a P node (N7P / N5P) a year later, then finally a nodelet that brings some improvements to density (N6 / N4). N3 seems to buck this trend somewhat.

N3E while feature improved manufacturing process window, with better performance, power, and yield. Volume production of N3E is scheduled for one year after N3.
N3E is an improvement. Improvement in that the manufacturing window. However, the majority in the design rule or something is similar. We're using the N3E to enhance the manufacturing window
From N3 to N3E we provide a better value on the transistor performance and have a better manufacturing window. As for the cost, they are similar. But we think our customers will enjoy a better yield, better defect density, and better transistor performance.
Dr. C. C. Wei – TSMC CEO

3 different quotes from today. It seems very much like a P type nodelet, but with an emphasis on manufacturing cycle times. TSMC seems to recognize N3 wafers will take so long to fab that they need to focus the improvements on tightening that up. P we always thought stood for plus, power, or performance. That was of course, speculation, but what does E mean? Efficiency? TSMC isn’t the type of company to make naming decisions willy nilly.

The hiccup on N3 brings many questions about TSMC’s competitive positioning versus Intel 20A and Samsung 2nm. Both these nodes are very aggressive and aimed at getting back into a competitive position against TSMC. Intel and Samsung even claim the nodes will bring leadership.

For TSMC, we are confident that we'll be very competitive, and we do have a very competitive schedule actually, let me say that, in our 3 - nanometer technology and 2 - nanometer technology.
And I can share with you that in our 2-nanometer technology is the density and performance will be the most competitive in 2025.
Dr. C. C. Wei – TSMC CEO

These are very reassuring statements about TSMC maintaining their lead. SemiAnalysis believes that TSMC will continue to be the most efficient, and best foundry in 2025, but their lead may be diminished. The big thing to note about this statement is that TSMC said most competitive in 2025. TSMC didn’t directly say their 2nm technology is 2025, but it sure sounds like it. That would be at minimum another 2.5 year gap between nodes just like it was for N5 to N3. Given that Apple is generally the ramp partner, this gap makes the most sense. While we believe TSMC remains ahead, this slowdown in node transitions is the perfect opportunity for Intel and Samsung to narrow the gap. Interesting times ahead!

There are a few other interesting details to come out of TSMC’s comments.

Our capital investment decisions are based on four disciplines; technology leadership, flexible and responsive manufacturing, retaining customers' trust and earning the proper return.
At the same time, we faced manufacturing cost challenges due to an increase in process complexity at leading node, new investment in mature notes, expansion of our global manufacturing footprint, and rising material in basic commodity cost. As we continue to work closely with our customers to support their goals, our pricing strategy will remain strategic, not opportunistic, to refer to our value creation
Even us, we shoulder a greater burden of investment for the industry, by taking such actions we believe we can achieve a proper return that enables us to invest to support our customers growth and deliver long term profitable goals with 50% and higher gross margin for our shareholders.
Dr. C. C. Wei – TSMC CEO

Costs are going up for new nodes, but TSMC is passing that cost along. Semiconductor capital equipment companies will party, but everyone else down stream will have to deal with the fact that cost per transistor is rising. TSMC is going to make their >=50% gross margin regardless of their costs.

In the past, there was only 1 or 2 customers providing the prepayments. But as we've been talking about now, we expect to invest higher capacity, higher capital expenditures in the next few years to satisfy the strong demand. And in order to secure our customers' commitment, we are able to secure the prepayments for some of those customers, and the number of the customer, I cannot disclose, but it's more than before.
We do not consider a JV with governments. However, JV with other Companies or key customers can be considered on a case-by-case basis.
Dr. C. C. Wei – TSMC CEO

As costs for new fabs skyrockets, TSMC is sharing the costs with customers. In the past, 1 or 2 large customers seemed to share the burden via prepayments for new fabs. SemiAnalysis believes this was Apple and Huawei. Now it seems like TSMC is increasing that number and involving many more major customers. The new fab in Japan is likely an example of this. Japan is providing subsidies, but they have no stake in the new fab. The comment on JV with other companies and key customers raises eyebrows. SemiAnalysis believes this is a partnership with Sony and Renesas. This fab will use the 28nm and 22nm nodes. It sounds like this fab will be geared towards automotive and 3D Stacked CMOS image sensors. Renesas and Sony manufacture these in house but want to move to more external due to sub-scale inefficiencies.